From 2025 to 2026, new trends will emerge in the semiconductor equipment industry. A group of semiconductor equipment manufacturers are intensively launching new equipment for square substrates, ranging from photolithography, measurement, CMP, stripping, and electroplating to laser through holes, slit coating, and glass metallization. "Panel Level Packaging, PLP" (Panel Level Packaging, PLP) is forming a new segmented track on the equipment side. This time, domestic equipment manufacturers were not absent.

Advanced packaging begins to “turn the circle into a square”

A report released by SEMI shows that global semiconductor equipment shipments increased by 14% year-on-year in the first quarter of 2026, reaching US$36.55 billion, a month-on-month increase of 1%. Record quarterly sales were driven by continued AI-related investments, including capacity expansion and technology upgrades to support advanced logic chips, DRAM and advanced packaging.

CoWoS (Chip-on-Wafer-on-Substrate) is the current mainstream solution for global AI/HPC high-end chip packaging. CoWoS will occupy 69% of the market share of 2.5D/3D advanced packaging technology in 2025. This technology is a 2.5D advanced packaging technology developed and led by TSMC. The technology was announced in 2011. Its core is to integrate heterogeneous chips such as logic chips and high-bandwidth memory (HBM) through silicon interposers, and then interconnect them with organic substrates to achieve high-density, high-performance system-level integration, which can effectively increase bandwidth, reduce power consumption and delay. CoWoS is currently mainly used in fields such as artificial intelligence (AI), high-performance computing (HPC) and data centers. This technology is widely used in many high-end AI chips from NVIDIA, AMD, Google and other companies.

In addition, as AI chips become larger and more complex in design, the area utilization and packaging efficiency of traditional circular wafers are gradually limited. Therefore, the trend is to "replace circles with squares", replacing wafers with panels, arranging the chips on a rectangular substrate, and finally connecting them to the underlying carrier board through the packaging process, so that multiple chips can be packaged together, which is CoPoS (Chip-on-Panel-on-Substrate).

The core technical advantage of panel-level packaging is to replace circular wafers with square panels, thus greatly improving material utilization. Taking a standard 610mm × 457mm printed circuit board as an example, its area is approximately 4 times the area of ​​a 300mm wafer. Theoretically, four times the number of wafer-level packages can be manufactured in a single batch. In addition, the chip itself is square, and by arranging it on a rectangular panel substrate, space utilization is further optimized compared to the wasted edges of a circular wafer.

The semiconductor industry follows the rule of "one generation of materials, one generation of technology, one generation of equipment". As advanced packaging "replaces circles with squares", equipment manufacturers' front-end layout has been fully launched.

International giants lay out panel-level packaging

Panel-level packaging requires substrate preparation, photoresist coating, exposure/photolithography, development, descum, seed layer deposition, electroplating, CMP planarization, TGV through holes, through hole metallization, measurement and inspection, etc. The process chain seems similar to that of wafer-level packaging (WLP), but in fact each step is different. In order to match larger warpage, larger area, and larger material deformation, almost every type of equipment from coating to inspection needs to be redesigned for panel-level packaging.

In this process chain, international giants have taken the lead in taking the lead. Relying on their technological accumulation in the field of wafer-level equipment, international giants are deploying full-chain processes and building ecological barriers.

Lithography and Metrology: Onto Innovation’s JetStep S3500 lithography system is designed for panel-level advanced packaging production. The system can handle chip offset caused by placement accuracy errors, CTE (coefficient of thermal expansion) mismatch and panel warpage. It has a large exposure field (59.4 × 59.4 mm) and a resolution of up to 2/2 μm line width/line space (L/S), with an option to increase the resolution to 1/1 μm. In addition, the system supports multiple exposure wavelengths, making it ideal for process development using new photopolymers. Application-specific options include warped panel handling, real-time optical focus, and chip offset correction to ensure panel-level packaging accuracy and reliability. ASML, Nikon Canon, Ushio, SCREEN and other manufacturers are also laying out related products.

RDL device:Manz Asia Technology successfully delivered the world’s first 310mm × 310mm panel-level packaging (PLP) electrochemical deposition (ECD) mass production equipment. The new ECD platform can flexibly support glass and metal square carriers, and integrates key wet process technologies of the redistribution layer (RDL) to provide mass production solutions for advanced packaging architectures such as FOPLP, CoPoS, and TGV. With ECD equipment as the core, Manz Asia Intelligent Technology has further integrated key wet process equipment such as cleaning, development, etching and stripping, and supports dual process modes of rotating spray (Spin) and surface spray (Spray) to form a complete panel-level RDL process solution Omni 310x. Omni 310x (310mm × 310mm) officially joins the existing Omni 510x (510mm × 515mm) and Omni 700x (700mm × 700mm) series, forming a complete panel-level mass production platform layout. Through the modular design architecture and flexible automation integration capabilities, customized configurations can be carried out according to different customers' product architecture, packaging technology and production capacity requirements, providing a more flexible technology path to support various stages of needs from R&D verification, trial production to mass production.

Laser via:The German TRUMPF Group and the German SCHMID Group cooperated to develop the "laser etching + wet chemical treatment" process. This process first uses TRUMPF's TruMicro series ultra-short pulse laser and TOP Cleave glass processing special laser focusing head to selectively modify the glass; then etching solution is used to etch away the laser-modified area to generate the required high-precision through holes.

In addition, frontline equipment giants such as Applied Materials, Lam Research, TEL, and KLA have all included panel-level packaging in their advanced packaging strategies.

Domestic equipment is intensively "handed in"

While international giants are building ecological barriers, domestic equipment manufacturers are not absent, seizing tickets for new tracks. From 2025 to 2026, domestic equipment manufacturers are moving from "verification" to "shipment" at the key process nodes of panel-level packaging.

Huahai Qingke won the first mass production order in China

In panel-level packaging, the CMP process directly determines the flatness, defect level and interface quality of the dielectric layer and metal layer, and is the core link to ensure interconnect reliability and final chip performance and yield. Master-P510APEX, China's first 510*515mm fully automatic board-level CMP mass production equipment independently developed by Huahai Qingke, has successfully received orders from important customers in the advanced packaging field and will be put into mass production applications in client production lines as planned. This marks a key breakthrough for domestic high-end equipment in advanced packaging core processes, and is also an important milestone in the extension of Huahai Qingke’s CMP equipment technology from the wafer level to the board level.

Northern Huachuang releases special process equipment for board-level packaging, and the first panel-level packaging Descum equipment leaves the factory

In the semiconductor manufacturing process, the Descum process is an important link that affects product yield and production efficiency. Recently, North Huachuang's first 600mm×600mm panel-level packaging debonding equipment (Descum) was successfully shipped from the factory.

Its board-level packaging Descum equipment is mainly used for dry processes such as plasma debonding, residue removal, surface modification and treatment in the field of board-level packaging. It can handle substrates with a maximum size of 600mm×600mm. For high-temperature sensitive materials such as PI, PR, and ABF, the board-level packaging Descum equipment is equipped with an active cooling system, which can stably control the substrate temperature within 75°C, greatly improving the yield rate. The equipment is based on dynamic electrode spacing adjustment technology, which can optimize the plasma distribution state in real time according to the different process requirements of PI, PR, ABF and other materials. This not only makes the degumming effect on the large plate highly uniform and consistent, but also broadens the process window; it also significantly shortens the single batch process time and allows higher unit output.

In addition to the glue removal equipment, the board-level packaging PVD equipment released by Northern Huachuang in March this year is dedicated to the TGV and RDL processes in the field of board-level packaging. It supports the deposition of metals such as adhesion layers and seed layers, and can handle substrates with a maximum size of 600mm × 600mm. The board-level packaging PVD equipment adopts the large-capacity cluster architecture independently designed by Northern Huachuang Vacuum. Based on the mature large-warp substrate transmission system control, it can mount up to 10 chambers at the same time, significantly optimizing space occupation while achieving high integration. For different process routes, the equipment can flexibly mount a variety of chambers such as PVD, Degas, Preclean, Flipper and Cooling to meet diverse coating needs. The excellent magnetic field control scheme can achieve ultra-high target utilization and effectively reduce consumable costs. At the same time, high deposition efficiency greatly increases the production capacity of a single equipment.

The board-level packaging PIQ equipment released at the same time is developed based on wafer-level PIQ technology. It is mainly used for the PI photoresist curing process in the field of board-level packaging. It can handle substrates with a maximum size of 510mm×515mm. The board-level packaging PIQ equipment adopts vertical large-diameter furnace heating technology, which can control the temperature uniformity within ±3°C, ensuring the PI curing quality from the source. The self-developed oxygen control and particle technology can quickly control the oxygen content in the process chamber and loading area to less than 10 ppm. The particle control reaches the wafer level, effectively preventing PI oxidation and ensuring the performance of the film layer, while providing more possibilities for exploring precision packaging processes with smaller line widths.

Shengmei Shanghai card position wet method and electroplating

Electroplating equipment is used in processes such as RDL (Redistribution Layer) manufacturing and TSV (Through Silicon Via) filling in advanced packaging. In 2025, Ame Shanghai will deliver the first horizontal panel electroplating equipment, Ultra ECP ap-p, to panel manufacturing customers. The system adopts ACM patented horizontal electroplating technology and supports multi-material electroplating processes such as copper, nickel, tin-silver and gold. Among them, the copper plating chamber is equipped with high-speed plating paddles specially designed for high-protrusion applications, which can achieve a protrusion height of more than 300 microns. Ultra ECP ap-p equipment uses a four-sided sealed dry contact chuck to improve reliability, is equipped with an in-chamber cleaning function to minimize chemical cross-contamination between different plating chambers, and adopts a horizontal plating design that achieves excellent film thickness uniformity by synchronously rotating the chuck and rotating rectangular electric field.

It also received an order for a panel-level advanced packaging negative pressure cleaning equipment from a global leading semiconductor packaging manufacturer outside mainland China, which will be delivered in the first quarter of 2026. The panel-level advanced packaging equipment order obtained this time is the Ultra C vac-p panel-level negative pressure cleaning equipment independently developed by AMC (global patent application pending). It is specially designed to cope with the stringent process requirements brought about by advanced fan-out panel-level packaging (FOPLP) and fine-pitch interconnection. This equipment improves impurity cleaning efficiency and process uniformity through the penetration ability of chemical liquid in a vacuum environment, ensuring the yield and reliability of complex 2.5D and 3D integration solutions. The device supports panel sizes of 310x310mm, 510x515mm, 600x600mm and other sizes, which can meet the large-scale mass production needs of next-generation device architecture.

Han's Semiconductor and Dier Laser Layout Laser Through-hole TGV Equipment

Glass substrates are regarded as the core carrier of next-generation AI packaging by giants such as NVIDIA, Intel, and Samsung due to their ultra-low warpage, high insulation, and excellent thermal stability. TGV through-hole equipment is the first hurdle for mass production of glass substrates.

The TGV glass through-hole equipment developed by Han's Semiconductor is the earliest equipment developed in China and has been stably used in TGV mass production. It can realize the preparation of blind holes, special-shaped holes and tapered holes of various sizes.

On May 22, 2026, Dier Laser stated that the company's TGV equipment used in semiconductor chip packaging, display chip packaging and other fields has completed the shipment of panel-level glass substrate through-hole equipment, achieving full coverage of wafer-level and panel-level TGV packaging laser technology.

Guihua and Baoding Jingtong Electromechanical complete key puzzle pieces

The process chain of panel-level packaging is extremely long. In addition to exposure, PVD, electroplating and other processes, coating and metallization are also key links that determine yield.

Guihua's slit coating equipment is specifically designed to meet the large-area photoresist coating requirements for panel-level packaging. It can achieve micron-level uniform coating on ultra-large substrates, laying the foundation for subsequent fine patterning of RDL (redistribution layer).

Baoding Jingtong Electromechanical has developed a 515×510mm glass substrate double-sided polished copper-nickel technology, which is a large-size glass substrate metallization core process for advanced packaging (2.5D/3D, Chiplet). Its core lies in the realization of a copper-nickel composite metal layer on the glass surface that is simultaneously polished at the nanoscale on both sides. It has high adhesion, high uniformity, and low stress. It can achieve thick copper grinding on both sides of the glass substrate, retaining a flawless and highly flat vertical through hole surface of more than 1:15, laying a high yield foundation for the next step of high-density wiring. At present, the equipment has passed the glass substrate customer assessment.

Why "another new track"?

The traditional advanced packaging equipment market has long been monopolized by a few international giants. However, in the field of panel-level packaging, due to relatively new technical routes and dispersed customer demands, domestic equipment manufacturers have gained a rare opportunity to start simultaneously. More importantly, panel-level packaging is naturally related to the display panel process. TSMC and Innolux even directly purchased old LCD factories and transformed them into panel-level packaging production lines, because the photoresist coating, exposure, development and other steps in the LCD process are highly similar to RDL manufacturing. This provides a group of equipment manufacturers that originally served the display industry with a springboard to cross-border entry into the high-end semiconductor market. These factors have prompted domestic equipment manufacturers to target this track and make early arrangements. Despite the enthusiasm of equipment manufacturers, panel-level packaging is still far from the stage of large-scale production.

The overall yield rate of current panel-level packaging is still lower than that of wafer-level packaging, and the non-uniform panel sizes make it difficult for equipment manufacturers to dilute R&D costs through standardized mass production. What's more serious is that despite rapid progress on the equipment side, materials, EDA tools, and testing standards are still relatively lagging behind. This means that the panel-level packaging equipment market will still be in the stage of small batch verification and multi-category coexistence in the short term. Whoever can take the lead in establishing irreplaceability at a certain key process node will be able to take the lead in the large-scale period.

The central narrative of device innovation over the past two decades has been Moore’s Law. But in the AI ​​era, when the increase in computing power of a single chip encounters physical limits, packaging becomes the key to continued performance growth, and panel-level packaging becomes one of the best solutions to reduce advanced packaging costs and break through production bottlenecks. The next incremental market for semiconductor equipment may be hidden in these square panels. This time, domestic equipment manufacturers have already got the tickets.